A semiconductor package is incorporated with at least one integrated circuit component such as semiconductor chip and preferably made compact in size. In response to this goal, a chip scale package (CSP) is desirably developed whose size is equal to or only slightly larger than the size of the semiconductor chip.
A conventional CSP is illustrated in FIG. 3 which directly fabricates a plurality of build-up layers on a semiconductor chip without using a chip carrier such as substrate or lead frame for accommodating the chip. As shown, the plurality of build-up layers are formed on an active surface 100 of the chip 10, including: a dielectric layer 11 disposed over the active surface 100 of the chip 10 and formed with a plurality of vias 110 by which bond pads 101 on the chip 10 are exposed; and a plurality of conductive traces 12 formed on the dielectric layer 11 and electrically connected to the exposed bond pads 101 of the chip 10. A solder mask layer 13 is applied over the conductive traces 12 and formed with a plurality of openings 130, allowing predetermined portions of the conductive traces 12 to be exposed via the openings 130 and bonded to solder balls 14 which serve as input/output (I/O) connections for the package to be electrically connected to an external device (not shown). This CSP structure, however, is defective of not able to provide more surface area, which is limited in accordance with the chip size, for accommodating more solder balls required for the external electrical connection.
Accordingly, another package structure with build-up layers formed on an encapsulated chip is disclosed in U.S. Pat. No. 6,271,469 to provide additional surface area for external I/O connections. As shown in FIG. 4, this package structure utilizes an encapsulant 15 to encapsulate a non-active surface 102 and side surfaces 103 of the chip 10, making the active surface 100 of the chip 10 exposed and flush with a surface 150 of the encapsulant 15. After the dielectric layer 11 (hereinafter referred to as “first dielectric layer”) and conductive traces 12 (hereinafter referred to as “first conductive traces”) are formed on the chip 10, a second dielectric layer 16 is disposed over the first conductive traces 12 and formed with a plurality of vias 160 to expose predetermined portions of the first conductive traces 12 by the vias 160. A plurality of second conductive traces 17 are formed on the second dielectric layer 16 and electrically connected to the exposed portions of the first conductive traces 12. Then, the solder mask layer 13 is applied over the second conductive traces 17, allowing predetermined portions of the second conductive traces 17 to be exposed via the openings 130 of the solder mask layer 13 and bonded to the solder balls 14.
However, a significant drawback incurred by the above semiconductor packages is that when a laser drilling technique is utilized to form vias through the first dielectric layer, positions of the bond pads on the chip, covered by the first dielectric layer, cannot be easily and precisely recognized by laser, making the vias not able to accurately correspond to the positions of the bond pads. As a result, the bond pads on the chip cannot be completely exposed, thus degrading electrical connection between the conductive traces and the incompletely-exposed bond pads and also damaging yield of the fabricated packages.
Therefore, the problem to be solved herein is to provide a semiconductor package with build-up layers formed on a chip by which bond pads on the chip can be precisely exposed and electrically connected to conductive traces to thereby improve fabrication yield of the semiconductor package.